1. Field of the Invention
This invention relates to computer systems and more particularly to instruction handling circuitry in computer systems.
The invention finds particular utility in computer systems where instructions are fetched a byte at a time and bytes are fetched successively to completely fetch an instruction. In such computer systems it has been the practice to fetch one instruction byte per machine cycle. This was accomplished by accessing storage during a first portion and updating the storage address during a second portion of the machine cycle. The instruction byte or segment retrieved from storage is entered into a selected register of the CPU. For example, the first byte of an instruction which is fetched is usually the operation code (OP code) byte and it is entered into the operation register. The IAR is updated and then the next byte of the instruction is fetched and placed into another register. The process continues until all bytes of the instruction are fetched and placed into appropriate registers in the CPU. This process is called the I phase or I fetch. The instruction is then executed according to the operation specified by the OP code. The execution of an instruction is the E phase.
2. Description of the Prior Art
The prior art techniques for speeding up the instruction processing rate include pre-fetching instructions so as to overlap instruction fetch and instruction execution phases. Another technique is to fetch more bytes of the instruction at any one time. These prior art techniques are effective but are relatively more expensive. This is because they require many parallel paths or wider paths for data as well as attendant control circuitry. In the present invention there is one additional data path, one additional register, and an auxiliary ALU together appropriate controls; however, the data paths, except for the paths from the additional register and auxiliary ALU, are one byte or segment wide. The present invention fetches only one byte or segment of the instruction at a time; however, because of the additional data path from storage; i.e., one that bypasses the register which feeds the regular ALU, it is possible to enter the fetched byte in the destination register, such as the OP register, faster. The auxiliary ALU can update the IAR in one operation and hence the IAR can be updated earlier witin a machine cycle. This only involves using an earlier clock signal for clocking the IAR. With the IAR updated earlier it is possible to initiate and complete a second storage access within the same machine cycle. Since the bytes are still fetched successively, the data path to the destination registers did not have to be widened.